The present invention relates generally to the field of semiconductor wafer fabrication equipment useful in the manufacture of semiconductor devices, more particularly to apparatus for depositing an epitaxial layer from a source gas by the chemical vapor deposition (CVD) method, and especially to improvements in the design of a refractory susceptor for use in supporting semiconductor substrates in an epitaxial deposition apparatus.
Apparatus of the above type is used in the fabrication of semiconductor devices on 100 millimeter or larger wafers of silicon. Epitaxial layers are formed on the surfaces of the wafers by heating them to temperatures in the region of 1100 to 1200 degrees Celsius in a bell jar containing a gaseous atmosphere consisting of a hydrogen carrier gas mixed with one or more reactive gases such as a silicon source gas or a dopant source gas.
During the various processing steps involved in the production of finished wafers, the semiconductor substrates are supported on a susceptor made of graphite which has been coated with silicon carbide. Such susceptors are formed as a hollow, elongate body having a polygonal cross-sectional shape by being milled from a solid block of graphite. The wall thickness of the susceptor has been on the order of 0.200 inch to provide sufficient strength to withstand normal handling and thermal cycling.
The susceptor together with the wafers supported on it must be heated to the high processing temperatures before processing can begin. The time and power input required to raise the temperature of the susceptor and substrates is largely dependent on the thermal mass of the susceptor, since the thermal mass of the substrates is relatively small.
Consequently, it would be very desirable to reduce the thermal mass of the susceptor in order to reduce the time and energy required to heat it to processing temperatures. At the same time, the quantity of hydrogen carrier gas consumed in processing operations would also be reduced. The net effect of such changes would be an increase in wafer throughput and a reduction in processing cost per wafer.